/*
 * Copyright (C) 2010 Texas Instruments
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
 * ----------------------------------------------------------------------------
 *
 */

#ifndef _DDR_DEFS_TI814X_H
#define _DDR_DEFS_TI814X_H

#include <asm/arch/hardware.h>

/* DDR Phy MMRs OFFSETs */
#define CMD0_REG_PHY_CTRL_SLAVE_RATIO_0		0x01C
#define CMD0_REG_PHY_DLL_LOCK_DIFF_0		0x028
#define CMD0_REG_PHY_INVERT_CLKOUT_0		0x02C
#define CMD1_REG_PHY_CTRL_SLAVE_RATIO_0		0x050
#define CMD1_REG_PHY_DLL_LOCK_DIFF_0		0x05C
#define CMD1_REG_PHY_INVERT_CLKOUT_0		0x060
#define CMD2_REG_PHY_CTRL_SLAVE_RATIO_0		0x084
#define CMD2_REG_PHY_DLL_LOCK_DIFF_0		0x090
#define CMD2_REG_PHY_INVERT_CLKOUT_0		0x094

/* DDR0 Phy MMRs */
#define CMD0_REG_PHY0_CTRL_SLAVE_RATIO_0	(0x01C + DDR0_PHY_BASE_ADDR)
#define CMD0_REG_PHY0_DLL_LOCK_DIFF_0		(0x028 + DDR0_PHY_BASE_ADDR)
#define CMD0_REG_PHY0_INVERT_CLKOUT_0		(0x02C + DDR0_PHY_BASE_ADDR)
#define CMD1_REG_PHY0_CTRL_SLAVE_RATIO_0	(0x050 + DDR0_PHY_BASE_ADDR)
#define CMD1_REG_PHY0_DLL_LOCK_DIFF_0		(0x05C + DDR0_PHY_BASE_ADDR)
#define CMD1_REG_PHY0_INVERT_CLKOUT_0		(0x060 + DDR0_PHY_BASE_ADDR)
#define CMD2_REG_PHY0_CTRL_SLAVE_RATIO_0	(0x084 + DDR0_PHY_BASE_ADDR)
#define CMD2_REG_PHY0_DLL_LOCK_DIFF_0		(0x090 + DDR0_PHY_BASE_ADDR)
#define CMD2_REG_PHY0_INVERT_CLKOUT_0		(0x094 + DDR0_PHY_BASE_ADDR)

#define DATA0_REG_PHY0_RD_DQS_SLAVE_RATIO_0	(0x0C8 + DDR0_PHY_BASE_ADDR)
#define DATA0_REG_PHY0_WR_DQS_SLAVE_RATIO_0	(0x0DC + DDR0_PHY_BASE_ADDR)
#define DATA0_REG_PHY0_WRLVL_INIT_RATIO_0	(0x0F0 + DDR0_PHY_BASE_ADDR)
#define DATA0_REG_PHY0_WRLVL_INIT_MODE_0	(0x0F8 + DDR0_PHY_BASE_ADDR)
#define DATA0_REG_PHY0_GATELVL_INIT_RATIO_0	(0x0FC + DDR0_PHY_BASE_ADDR)
#define DATA0_REG_PHY0_GATELVL_INIT_MODE_0	(0x104 + DDR0_PHY_BASE_ADDR)
#define DATA0_REG_PHY0_FIFO_WE_SLAVE_RATIO_0	(0x108 + DDR0_PHY_BASE_ADDR)
#define DATA0_REG_PHY0_WR_DATA_SLAVE_RATIO_0	(0x120 + DDR0_PHY_BASE_ADDR)
#define DATA0_REG_PHY0_USE_RANK0_DELAYS		(0x134 + DDR0_PHY_BASE_ADDR)
#define DATA0_REG_PHY0_DLL_LOCK_DIFF_0		(0x138 + DDR0_PHY_BASE_ADDR)

#define DATA1_REG_PHY0_RD_DQS_SLAVE_RATIO_0	(0x16C + DDR0_PHY_BASE_ADDR)
#define DATA1_REG_PHY0_WR_DQS_SLAVE_RATIO_0	(0x180 + DDR0_PHY_BASE_ADDR)
#define DATA1_REG_PHY0_WRLVL_INIT_RATIO_0	(0x194 + DDR0_PHY_BASE_ADDR)
#define DATA1_REG_PHY0_WRLVL_INIT_MODE_0	(0x19C + DDR0_PHY_BASE_ADDR)
#define DATA1_REG_PHY0_GATELVL_INIT_RATIO_0	(0x1A0 + DDR0_PHY_BASE_ADDR)
#define DATA1_REG_PHY0_GATELVL_INIT_MODE_0	(0x1A8 + DDR0_PHY_BASE_ADDR)
#define DATA1_REG_PHY0_FIFO_WE_SLAVE_RATIO_0	(0x1AC + DDR0_PHY_BASE_ADDR)
#define DATA1_REG_PHY0_WR_DATA_SLAVE_RATIO_0	(0x1C4 + DDR0_PHY_BASE_ADDR)
#define DATA1_REG_PHY0_USE_RANK0_DELAYS		(0x1D8 + DDR0_PHY_BASE_ADDR)
#define DATA1_REG_PHY0_DLL_LOCK_DIFF_0		(0x1DC + DDR0_PHY_BASE_ADDR)

#define DATA2_REG_PHY0_RD_DQS_SLAVE_RATIO_0	(0x210 + DDR0_PHY_BASE_ADDR)
#define DATA2_REG_PHY0_WR_DQS_SLAVE_RATIO_0	(0x224 + DDR0_PHY_BASE_ADDR)
#define DATA2_REG_PHY0_WRLVL_INIT_RATIO_0	(0x238 + DDR0_PHY_BASE_ADDR)
#define DATA2_REG_PHY0_WRLVL_INIT_MODE_0	(0x240 + DDR0_PHY_BASE_ADDR)
#define DATA2_REG_PHY0_GATELVL_INIT_RATIO_0	(0x244 + DDR0_PHY_BASE_ADDR)
#define DATA2_REG_PHY0_GATELVL_INIT_MODE_0	(0x24C + DDR0_PHY_BASE_ADDR)
#define DATA2_REG_PHY0_FIFO_WE_SLAVE_RATIO_0	(0x250 + DDR0_PHY_BASE_ADDR)
#define DATA2_REG_PHY0_WR_DATA_SLAVE_RATIO_0	(0x268 + DDR0_PHY_BASE_ADDR)
#define DATA2_REG_PHY0_USE_RANK0_DELAYS		(0x27C + DDR0_PHY_BASE_ADDR)
#define DATA2_REG_PHY0_DLL_LOCK_DIFF_0		(0x280 + DDR0_PHY_BASE_ADDR)

#define DATA3_REG_PHY0_RD_DQS_SLAVE_RATIO_0	(0x2B4 + DDR0_PHY_BASE_ADDR)
#define DATA3_REG_PHY0_WR_DQS_SLAVE_RATIO_0	(0x2C8 + DDR0_PHY_BASE_ADDR)
#define DATA3_REG_PHY0_WRLVL_INIT_RATIO_0	(0x2DC + DDR0_PHY_BASE_ADDR)
#define DATA3_REG_PHY0_WRLVL_INIT_MODE_0	(0x2E4 + DDR0_PHY_BASE_ADDR)
#define DATA3_REG_PHY0_GATELVL_INIT_RATIO_0	(0x2E8 + DDR0_PHY_BASE_ADDR)
#define DATA3_REG_PHY0_GATELVL_INIT_MODE_0	(0x2F0 + DDR0_PHY_BASE_ADDR)
#define DATA3_REG_PHY0_FIFO_WE_SLAVE_RATIO_0	(0x2F4 + DDR0_PHY_BASE_ADDR)
#define DATA3_REG_PHY0_WR_DATA_SLAVE_RATIO_0	(0x30C + DDR0_PHY_BASE_ADDR)
#define DATA3_REG_PHY0_USE_RANK0_DELAYS		(0x320 + DDR0_PHY_BASE_ADDR)
#define DATA3_REG_PHY0_DLL_LOCK_DIFF_0		(0x324 + DDR0_PHY_BASE_ADDR)

/* DDR1 Phy MMRs */
#define	CMD0_REG_PHY1_CTRL_SLAVE_RATIO_0	(0x01C + DDR1_PHY_BASE_ADDR)
#define	CMD0_REG_PHY1_DLL_LOCK_DIFF_0		(0x028 + DDR1_PHY_BASE_ADDR)
#define	CMD0_REG_PHY1_INVERT_CLKOUT_0		(0x02C + DDR1_PHY_BASE_ADDR)
#define	CMD1_REG_PHY1_CTRL_SLAVE_RATIO_0	(0x050 + DDR1_PHY_BASE_ADDR)
#define	CMD1_REG_PHY1_DLL_LOCK_DIFF_0		(0x05C + DDR1_PHY_BASE_ADDR)
#define	CMD1_REG_PHY1_INVERT_CLKOUT_0		(0x060 + DDR1_PHY_BASE_ADDR)
#define	CMD2_REG_PHY1_CTRL_SLAVE_RATIO_0	(0x084 + DDR1_PHY_BASE_ADDR)
#define	CMD2_REG_PHY1_DLL_LOCK_DIFF_0		(0x090 + DDR1_PHY_BASE_ADDR)
#define	CMD2_REG_PHY1_INVERT_CLKOUT_0		(0x094 + DDR1_PHY_BASE_ADDR)

#define	DATA0_REG_PHY1_RD_DQS_SLAVE_RATIO_0	(0x0C8 + DDR1_PHY_BASE_ADDR)
#define	DATA0_REG_PHY1_WR_DQS_SLAVE_RATIO_0	(0x0DC + DDR1_PHY_BASE_ADDR)
#define	DATA0_REG_PHY1_WRLVL_INIT_RATIO_0	(0x0F0 + DDR1_PHY_BASE_ADDR)
#define	DATA0_REG_PHY1_WRLVL_INIT_MODE_0	(0x0F8 + DDR1_PHY_BASE_ADDR)
#define	DATA0_REG_PHY1_GATELVL_INIT_RATIO_0	(0x0FC + DDR1_PHY_BASE_ADDR)
#define	DATA0_REG_PHY1_GATELVL_INIT_MODE_0	(0x104 + DDR1_PHY_BASE_ADDR)
#define	DATA0_REG_PHY1_FIFO_WE_SLAVE_RATIO_0	(0x108 + DDR1_PHY_BASE_ADDR)
#define	DATA0_REG_PHY1_WR_DATA_SLAVE_RATIO_0	(0x120 + DDR1_PHY_BASE_ADDR)
#define	DATA0_REG_PHY1_USE_RANK0_DELAYS		(0x134 + DDR1_PHY_BASE_ADDR)
#define	DATA0_REG_PHY1_DLL_LOCK_DIFF_0		(0x138 + DDR1_PHY_BASE_ADDR)

#define	DATA1_REG_PHY1_RD_DQS_SLAVE_RATIO_0	(0x16C + DDR1_PHY_BASE_ADDR)
#define	DATA1_REG_PHY1_WR_DQS_SLAVE_RATIO_0	(0x180 + DDR1_PHY_BASE_ADDR)
#define	DATA1_REG_PHY1_WRLVL_INIT_RATIO_0	(0x194 + DDR1_PHY_BASE_ADDR)
#define	DATA1_REG_PHY1_WRLVL_INIT_MODE_0	(0x19C + DDR1_PHY_BASE_ADDR)
#define	DATA1_REG_PHY1_GATELVL_INIT_RATIO_0	(0x1A0 + DDR1_PHY_BASE_ADDR)
#define	DATA1_REG_PHY1_GATELVL_INIT_MODE_0	(0x1A8 + DDR1_PHY_BASE_ADDR)
#define	DATA1_REG_PHY1_FIFO_WE_SLAVE_RATIO_0	(0x1AC + DDR1_PHY_BASE_ADDR)
#define	DATA1_REG_PHY1_WR_DATA_SLAVE_RATIO_0	(0x1C4 + DDR1_PHY_BASE_ADDR)
#define	DATA1_REG_PHY1_USE_RANK0_DELAYS		(0x1D8 + DDR1_PHY_BASE_ADDR)
#define	DATA1_REG_PHY1_DLL_LOCK_DIFF_0		(0x1DC + DDR1_PHY_BASE_ADDR)

#define	DATA2_REG_PHY1_RD_DQS_SLAVE_RATIO_0	(0x210 + DDR1_PHY_BASE_ADDR)
#define	DATA2_REG_PHY1_WR_DQS_SLAVE_RATIO_0	(0x224 + DDR1_PHY_BASE_ADDR)
#define	DATA2_REG_PHY1_WRLVL_INIT_RATIO_0	(0x238 + DDR1_PHY_BASE_ADDR)
#define	DATA2_REG_PHY1_WRLVL_INIT_MODE_0	(0x240 + DDR1_PHY_BASE_ADDR)
#define	DATA2_REG_PHY1_GATELVL_INIT_RATIO_0	(0x244 + DDR1_PHY_BASE_ADDR)
#define	DATA2_REG_PHY1_GATELVL_INIT_MODE_0	(0x24C + DDR1_PHY_BASE_ADDR)
#define	DATA2_REG_PHY1_FIFO_WE_SLAVE_RATIO_0	(0x250 + DDR1_PHY_BASE_ADDR)
#define	DATA2_REG_PHY1_WR_DATA_SLAVE_RATIO_0	(0x268 + DDR1_PHY_BASE_ADDR)
#define	DATA2_REG_PHY1_USE_RANK0_DELAYS		(0x27C + DDR1_PHY_BASE_ADDR)
#define	DATA2_REG_PHY1_DLL_LOCK_DIFF_0		(0x280 + DDR1_PHY_BASE_ADDR)

#define	DATA3_REG_PHY1_RD_DQS_SLAVE_RATIO_0	(0x2B4 + DDR1_PHY_BASE_ADDR)
#define	DATA3_REG_PHY1_WR_DQS_SLAVE_RATIO_0	(0x2C8 + DDR1_PHY_BASE_ADDR)
#define	DATA3_REG_PHY1_WRLVL_INIT_RATIO_0	(0x2DC + DDR1_PHY_BASE_ADDR)
#define	DATA3_REG_PHY1_WRLVL_INIT_MODE_0	(0x2E4 + DDR1_PHY_BASE_ADDR)
#define	DATA3_REG_PHY1_GATELVL_INIT_RATIO_0	(0x2E8 + DDR1_PHY_BASE_ADDR)
#define	DATA3_REG_PHY1_GATELVL_INIT_MODE_0	(0x2F0 + DDR1_PHY_BASE_ADDR)
#define	DATA3_REG_PHY1_FIFO_WE_SLAVE_RATIO_0	(0x2F4 + DDR1_PHY_BASE_ADDR)
#define	DATA3_REG_PHY1_WR_DATA_SLAVE_RATIO_0	(0x30C + DDR1_PHY_BASE_ADDR)
#define	DATA3_REG_PHY1_USE_RANK0_DELAYS		(0x320 + DDR1_PHY_BASE_ADDR)
#define	DATA3_REG_PHY1_DLL_LOCK_DIFF_0		(0x324 + DDR1_PHY_BASE_ADDR)

#define DATA_MACRO_0			0
#define DATA_MACRO_1			1
#define DATA_MACRO_2			2
#define DATA_MACRO_3			3
#define DDR_PHY0			0
#define DDR_PHY1			1

/* Common DDR PHY parameters */
#define	PHY_INVERT_CLKOUT_DEFINE		0
#define	DDR3_PHY_INVERT_CLKOUT_OFF		0
#define	PHY_REG_USE_RANK0_DELAY_DEFINE		0
#define	mDDR_PHY_REG_USE_RANK0_DELAY_DEFINE	1
#define	PHY_DLL_LOCK_DIFF_DEFINE		0x4
#define	PHY_CMD0_DLL_LOCK_DIFF_DEFINE		0x4
#define DDR_EMIF_REF_TRIGGER			0x10000000

#define	PHY_GATELVL_INIT_CS0_DEFINE		0x0
#define	PHY_WRLVL_INIT_CS0_DEFINE		0x0

#define	PHY_GATELVL_INIT_CS1_DEFINE		0x0
#define	PHY_WRLVL_INIT_CS1_DEFINE		0x0
#define	PHY_CTRL_SLAVE_RATIO_CS1_DEFINE		0x80

/* TI814X DDR2 PHY CFG parameters */
#define	DDR2_PHY_RD_DQS_CS0_DEFINE		0x35
#define	DDR2_PHY_WR_DQS_CS0_DEFINE		0x20
#define	DDR2_PHY_RD_DQS_GATE_CS0_DEFINE		0x90
#define	DDR2_PHY_WR_DATA_CS0_DEFINE		0x50
#define	DDR2_PHY_CTRL_SLAVE_RATIO_CS0_DEFINE	0x80

/* TI814X DDR3 PHY CFG parameters */
#define DDR3_PHY_RD_DQS_CS0_DEFINE		0x30
#define DDR3_PHY_WR_DQS_CS0_DEFINE		0x21
#define DDR3_PHY_RD_DQS_GATE_CS0_DEFINE		0xC0
#define DDR3_PHY_WR_DATA_CS0_DEFINE		0x44
#define DDR3_PHY_CTRL_SLAVE_RATIO_CS0_DEFINE	0x80

/* DDR0/1 IO CTRL parameters */
#define DDR0_IO_CTRL_DEFINE		0x00030303
#define DDR1_IO_CTRL_DEFINE		0x00030303

/* Initially set a large DDR refresh period */
#define DDR_EMIF_REF_CTRL		0x00004000

/* TI814X DDR2 EMIF CFG Registers values 333MHz*/
#define DDR2_EMIF_READ_LATENCY		0x07
#define DDR2_EMIF_TIM1			0x0AAAF552
#define DDR2_EMIF_TIM2			0x043631D2
#define DDR2_EMIF_TIM3			0x00000327
#define DDR2_EMIF_REF_CTRL		0x10000C30
#define DDR2_EMIF_SDRAM_CONFIG		0x40801AB2
#define DDR2_EMIF_SDRAM_ZQCR		0x50074BE1

/* TI814X DDR3 EMIF CFG Registers values 400MHz */
#define DDR3_EMIF_READ_LATENCY		0x00173209
#define DDR3_EMIF_TIM1			0x0AAAD4DB
#define DDR3_EMIF_TIM2			0x682F7FDA
#define DDR3_EMIF_TIM3			0x501F82BF
#define DDR3_EMIF_REF_CTRL		0x00000C30
#define DDR3_EMIF_SDRAM_CONFIG		0x61C011B2
#define DDR3_EMIF_SDRAM_ZQCR		0x50074BE1

/*
 * TI814X PG1.0 DMM LISA MAPPING
 * Two 256MB sections with 128-byte interleaved(hole in b/w)
 */
#define PG1_0_DMM_LISA_MAP__0		0x0
#define PG1_0_DMM_LISA_MAP__1		0x0
#define PG1_0_DMM_LISA_MAP__2		0x80440300
#define PG1_0_DMM_LISA_MAP__3		0xC0440300

/*
 * TI814X PG2.1 DMM LISA MAPPING
 * 1G contiguous section with 128-byte interleaving
 */
#define PG2_1_DMM_LISA_MAP__0		0x0
#define PG2_1_DMM_LISA_MAP__1		0x0
#define PG2_1_DMM_LISA_MAP__2		0x0
#define PG2_1_DMM_LISA_MAP__3		0x80640300

#endif  /* _DDR_DEFS_TI814X_H */

